Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, has announced the launch of its latest open process design kit (PDK), alongside a training program offered through EUROPRACTICE. The PDK will enable virtual digital designs in imec’s N2 technology, including backside power delivery network. The PDK will be embedded in EDA tool suites, such as from Cadence Design Systems and Synopsys, providing broad access to advanced nodes for design pathfinding, system research and training.
The PDK will give academia and industry the tools to train the semiconductor experts of tomorrow and enable the industry to transition their products into next generations technologies through meaningful design pathfinding. Foundry PDKs give chip designers access to a library of tested and proven components to deliver functional and reliable designs. These are usually available to the ecosystem once the technology reaches a critical level of manufacturability. However, restricted access and the need for NDAs have created a high threshold for academia and industry to access advanced technology nodes during their development.
The design pathfinding PDK contains the necessary infrastructure for digital design based on a set of digital standard cell libraries and SRAM IP macros. In the future, the design pathfinding PDK platform will extend to more advanced nodes (e.g. A14). The training program will start early Q2, teaching subscribers the specificities of the N2 technology node and offering hands-on training on digital design platforms using the Cadence and the Synopsys EDA software.
The N2 technology node is based on nanosheet devices, which are expected to offer superior performance, power and area scaling compared to FinFETs. Nanosheet devices consist of multiple horizontal stacked nanosheets that can be individually controlled, allowing for more design flexibility and optimization. The backside power delivery network is a novel approach to reduce the power and performance bottleneck caused by the increasing resistance of the interconnects. By routing the power and ground signals through the backside of the wafer, the parasitic resistance and capacitance can be significantly reduced, leading to faster and more energy-efficient circuits.
The following table summarizes some of the key features and benefits of the N2 technology node and the design pathfinding PDK:
| Feature | Benefit |
|---|---|
| Nanosheet devices | Superior performance, power and area scaling |
| Backside power delivery network | Reduced parasitic resistance and capacitance |
| Open access and training | Lowered threshold for academia and industry |
| Design pathfinding | Early exploration and optimization of future products |
| EDA tool integration | Seamless design flow and verification |
Imec’s design pathfinding PDK is an excellent example of how industry partnerships can broaden access to advanced process technology for the current and next generation of designers to accelerate their semiconductor innovation. “If we want to engage a new generation of chip designers, we must provide them early access to the infrastructure needed to develop their design skills on the most advanced technology nodes. The accompanying training courses will get these designers up to speed as quickly as possible and acquaint them with the most recent technology disruptions such as nanosheet devices and wafer backside technology. The design pathfinding PDK will also help companies to transition their designs to future technology nodes and pre-empt scaling bottlenecks for their products.” says Julien Ryckaert, VP Logic Technologies at imec.
