Process automation is the use of technology to automate and optimize various industrial processes, such as manufacturing, logistics, energy, and healthcare. Process automation relies on wireless communication systems to enable data transmission, remote control, and real-time monitoring of devices and machines. However, wireless communication systems face many challenges in terms of speed, latency, reliability, and scalability, especially in the era of beyond 5G (B5G), where new applications and services demand higher performance and quality of service.
One of the key components of wireless communication systems is the phase locked loop (PLL), which is a feedback circuit that synchronizes the frequency and phase of an output signal with a reference signal. PLLs are widely used for frequency synthesis, modulation, demodulation, and clock recovery in wireless transceivers and radar systems. However, PLLs also suffer from various sources of error and noise, which degrade the quality of the output signal and affect the overall system performance. One of the main sources of error and noise in PLLs is the fractional spur, which is an unwanted signal that arises from the periodicity in the error of the fractional division ratio. Fractional spurs appear as sidebands around the desired output frequency and cause phase noise, interference, and distortion in the output signal.
Fractional spurs are particularly problematic for fractional-N PLLs, which are a popular type of PLL that offer excellent resolution and flexibility of frequency control. Fractional-N PLLs use a fractional divider to divide the output frequency by a non-integer value, which allows for finer tuning of the output frequency. However, this also introduces a quantization error in the feedback loop, which results in fractional spurs. To mitigate this error, fractional-N PLLs typically use a digital-to-time converter (DTC) to cancel out the quantization error by adding or subtracting a small amount of time to the feedback signal. However, DTCs also have their own imperfections, such as integral non-linearities (INLs), which cause variations in the DTC output and ultimately manifest as fractional spurs.
Therefore, it is essential to develop new techniques and methods to combat fractional spurs in PLLs, especially for B5G applications that require high-performance wireless communication systems. In this article, we will review some of the recent advances and innovations in this field, and discuss how they can improve the wireless system performance in B5G process automation.
Cascaded-Fractional Divider Technique
One of the recent techniques to combat fractional spurs in PLLs is the cascaded-fractional divider technique, proposed by a research team from Tokyo Institute of Technology . This technique involves splitting the frequency control word (FCW), which is an internal PLL signal that controls the output frequency, into two parts, but in a way that both parts are far from an integer value. The logic behind this is that for far-integer FCWs, fractional spurs appear in higher frequencies, and high-frequency components are naturally filtered out by the inherent operations of the PLL. The cascaded-fractional divider technique also reduces the DTC gain, which is the amount of time added or subtracted by the DTC, and thus reduces the INL-induced fractional spurs.
The research team demonstrated the effectiveness of this technique by implementing a fractional-N PLL with a cascaded-fractional divider and comparing it with a conventional fractional-N PLL. The results showed that the proposed technique achieved a significant improvement in the fractional spur level, reducing it by more than 20 dB. The proposed technique also achieved a low power consumption of 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. The proposed technique is suitable for B5G applications that require high-resolution and low-spur frequency synthesis, such as radar systems and wireless transceivers.
Adaptive Algorithm for DTC Calibration
Another recent technique to combat fractional spurs in PLLs is the adaptive algorithm for DTC calibration, proposed by a research team from Zhejiang University . This technique involves using an adaptive algorithm to calibrate the DTC gain and suppress the fractional spurs. The adaptive algorithm is based on the least mean square (LMS) method, which is a widely used method for adaptive filtering and system identification. The LMS method iteratively updates the DTC gain based on the error signal, which is the difference between the desired output frequency and the actual output frequency. The LMS method minimizes the mean square error and converges to the optimal DTC gain that cancels out the quantization error and the fractional spurs.
The research team demonstrated the effectiveness of this technique by implementing an all-digital PLL with an adaptive algorithm for DTC calibration and comparing it with a conventional all-digital PLL. The results showed that the proposed technique achieved a significant improvement in the fractional spur level, reducing it by more than 30 dB. The proposed technique also achieved a low power consumption of 4.8 mW from a 1.2 V supply, which leads to a figure of merit of -241.6 dB. The proposed technique is suitable for B5G applications that require low-power and low-spur frequency synthesis, such as wireless sensor networks and IoT devices.
Comparison of the Two Techniques
The following table summarizes and compares the main features and performance metrics of the two techniques discussed above.
| Technique | FCW Splitting | DTC Gain | Fractional Spur Level | Power Consumption | Figure of Merit |
|---|---|---|---|---|---|
| Cascaded-Fractional Divider | Yes | Reduced | -70 dBc | 8.89 mW | -247.4 dB |
| Adaptive Algorithm for DTC Calibration | No | Adapted | -75 dBc | 4.8 mW | -241.6 dB |
As can be seen from the table, both techniques achieve a substantial improvement in the fractional spur level, which is the main objective of this article. However, they also have different trade-offs and advantages. The cascaded-fractional divider technique requires splitting the FCW into two parts, which may increase the complexity and cost of the PLL design. The adaptive algorithm for DTC calibration does not require splitting the FCW, but it requires an additional error signal and an adaptive filter, which may introduce some latency and overhead. The cascaded-fractional divider technique has a higher power consumption and a higher figure of merit than the adaptive algorithm for DTC calibration, which indicates that it has a better performance per power ratio. However, the adaptive algorithm for DTC calibration has a lower absolute power consumption, which may be more desirable for some applications that have strict power constraints.
